Cryogenic adder



Feb- 25, 1963 J. H. GRlEsMER ETAL 3,079,033

CRYOGENIC ADDER '7 Sheets-Sheet 1 Filed Jan. 19, 1960 Iota/w INVENTURS.JAMES H. GR|ESMER ERIC G. WAGNER BY- 7Zom @1MM-u- Feb l26, 1963 .1. I-I.GRIEsMER ErAI. I 3,079,033

CRYOGENIC ADDER Filed Jan. 19, 1960 '7 Sheets-Sheet 2 FIG. 4 FIG' 2 FIG.5 FIG. Gy

FIG. 7

FIG. 8

FIG. 3

Fb 25, 1963 J. H. GRIESMER ETAL 3,079,083

cRYoGEnIc ADDER REGISTER Feb- 26, 1963 J. H. GRlEsMER Erm. 3,079,033

CRYOGENIC ADDER 7 Sheets-Sheet 4 Filed Jan. 19, 1960 Feb. 26, 1963 J. H.GRIESMER AL cRYoGENIc Axa/15212@Vv Filed Jan. 19, 1960 7 Sheets-Sheet 5J. H. GRlEsMER ETAL 3,079,083

Feb. 26, 1963 CRYOGENIC ADDER T Sheets-Sheet 6 Filed Jan. 19, 1960 Feb.26, 1953 J. H. GRn-:SMER Erm. 3,079,083

' CRYOGENIC ADDER Filed Janf 19, 1960, v 7 sheets-sheet 7 I l* ZOSjIl"Cl I "In "Tl FIG. e C O V 1 T 304 x) 306 gjn 322B N26 Y l y 308 0 f* 32oK3@ l \334 \332 L QQ 324 n 35o 1 346A U l() Hvge l 1 3g 342 34o n In nonl' l" "O" o o o 24 p Q \CARRY STORAGE United States Patent iilice3,079,083 Patented Feb. 26, 1963 3,079,983 CRYGENiC ADDER James H.Griesmer, Ossining, and Eric G. Wagner, New

York, NX., assignors to International Business Machines Corporation, NewYork, NX., a corporation ot New York Fiied dan. 19, 196i), Ser. No.3,392 7 Claims. (Ci. 2235-176) The present invention relates to addingcircuits and more particularly to cryogenic adders employing inhibitorcircuitry.

The field of supercooled circuits (cryogenics) has found many newapplications in computer technology, and in numerous instances the useoi supercooled circuits with superconductive properties has proved moresatisfactory than the vacuum tubes, transistors or magnetic deviceshaving conventional acceptance. One of the basic superconductive devicesemployed in computer constructions is the cryotron. A cryotron may be afour terminal ,element including a straight wire placed inside a coil ofdifferent material and cooled to its superconductive temperature. Atthis temperature a very small voltage is sutiicient to induce apersistent current in the straight wire provided that no current ispresent in the coil. A current in the coil, however, Will produce amagnetic iield to change the superconductive properties of the straightwire and cause the persistent current to cease. Thus, the cryotronutilizes the fact that the superconductive transition of a materialdepends upon both temperature and electromagnetic field. The inherentcharacteristics of such a device enable it to perform switching andinhibiting functions which are readily adaptable to computerapplications.

An array of cryotrons may be constructed in which horizontal andvertical lines are arranged in a lattice configuration with the cryotronelements being connected in the array at the crossover or interactionpoints between the horizontal and Vertical lines. The cryotrons serve asinhibitors to control the currents applied to the array and therebyenable the array to perform certain logical functions.

In an illustrative arrangement according to this invention a serialadder uses rectangular array inhibitor logic. Signals from input storagedevices along with control signals from a stepping switch cause all butcertain lines of a cryotron adder input array to be inhibited. Currentsthrough the uninhibited lines serve as inputs to the adder array therebycausing current through certain output lines of the adder array to beinhibited. A carry input is applied to the adder array therebyinhibiting current in additional output lines of the adder array.Currents through the remaining output lines of the adder array appear assum and carry signals or bits. The carry bit is stored and subsequentlyapplied as an input to the adder array. The inhibiting action producedby a stepping switch permits the sum bit to be stored in a desiredstorage device. By this arrangement a small and compact adder isprovided which, because of the absence of resistance in the lines of theadder, requires very little control power and generates only a minimumamount of heat.

These and other features of this invention may be more fully appreciatedwhen considered in the light of the following speciiication and drawingsin which:

FlG. l is a block diagram of an adder employing the principles of thepresent invention;

FIG. 2 is a diagram of the relationships of FIGS. 4 through 8;

FIG. 3 is an illustration of inhibitor symbols used throughout thedrawings;

FIG. 4 illustrates the X and Y registers of the present invention;

FIG. 5 illustrates the adder input array and theupper half of thestepping switch of the present invention;

FIG. `6 is an illustration of the adder array constructed according tothis invention;

FIG. 7 illustrates the adder output array, the sum register and thelower half of the stepping switch according to this invention; and

FIG. 8 illustrates a carry storage circuit in accordance with thepresent invention. Y v

FG. l is a block diagram of a cryogenic adder constructed in accordancewith the principles of the present invention. The adder is illustratedand described as a serial binary adder. A binary number Xn (the denot-Ving the number of bits in the number X and consequently the number ofstorage devices within the X register as will be explained in greaterdetail hereinafter) is applied to the X register 10 which has n outputs.A number Yn which is to be added to the number Xn is applied to a Yregister 12 which has n outputs. The X and the Y `outputs of theregister 1t) and the register 12, respectively, are applied to an adderinput array 14. These input signals, along with the action vof astepping switch 16, cause certain paths to be inhibited and therebydetermine superconductive paths in the adder input array 1,4 throughwhich the X and Y bits or signals from the stages of the registers 10and V12 may be sequentially applied to an adder array 18. The adderarray 18 provides sum bits or signals S which, together with the actionof the stepping switch 16, control an adder output array 20 to store mbits (where m=n-{1) in a sum register 22. The adder array 18 alsoreceives a carry bit C from a carry storage circuit 24. The adder array18 generates a carry bit C' which is stored in the carry storage circuit24 during the addition of an X bit and a Y bit, and the carry storagecircuit 22 subsequently applies this carry bit C as the carry Ibit C tothe adder array 1S during the next succeeding addition of an X bit and aY bit. Inputs P and Q applied to the carry Vstorage circuit 24 cause thecarry bit C to bepstored and subsequently applied to the adder array 18as a carry bit C.

V FIG.V 3a illustrates the symbol used for an inhibitor in the circuitsillustrated in FIGS. 4through 8. Current through a line 3G inhibitscurrent through a line 32whenever there is an alternate superconductivepath for the current in the line 32. The action of the inhibitorillustrated in FIG. 3a will be readily apparent by reference to thesymbol for a wire wound inhibitor or cryotron shown in FIG. 3b. Theinhibitors illustrated in FIGS. 3a and 3c are equivalent to the wirewound gates shown in FIGS. 3b and 3d. Current through a winding 34 makesa gate 36 go resistive (normal) thereby blocking current through a line,3S whenever an alternate superconductive path is present. The inhibitorsymbol illustrated in FIG. 3c is the same as that illustrated in FIG. 3aexcept that it is rotatedv ninety degrees. Current through a verticalline 40 inhibits current through a horizontal line 42 whenever analternate superconductive path is present in the same mannerthat currentthrough a winding 44 of the cryotron symbol in FIG. 3d drives Isl gate46 normal thereby inhibiting current through a 'ne 4S.

Each of the gate lines of the cryotrons in the circuits disclosed hereinis constructed of a material which is in a superconductive state at t-heoperating temperature of the circuit in the absence of a magnetic iield,but which is driven resistive (normal) by a magnetic field produced whena current greater than a predetermined minimum or threshold currentexists in its control winding. The remaining portions of the circuit,that is,- the control scrapes windings and the connections between Vthevarious components are fabricated of a su-perconductor material whichremains in a superconductive state under all conditions of circuitoperation. For example, the gates may be constructed of tantalum andythe remaining portions of the circuit ymay be constructed of niobium,or other suitable materials, such as those discussed in the article byD. A. Buck, The Cryotron-A Superconductive Computer Component,Proceedings of the IRE, pp. 4S2-493g April 1956, may be employed.Film-type cryotrons are preferably employed in circuits constructed andoperated in accordance with the principles of the present invention. Fora detailed discussion of nini-type cryotrons and the manner in whichthey may be constructed, reference may be made to the copendingapplications, Serial No. 625,512 and Serial No. 765,760 filed onNovember 30, 1956, and October 7, 1958, respectively, both of which havebeen -assigned to the assignee of the present invention.

Referring `to FIG. 4, the X register and the Y register 12 areillustrated in detail. Each of the registers 10 and 12 includes threebistable storage devices such as flip-Hops. The register 19 includes yafirst stage ilip-ilop 50, a second stage flip-ilop 7i? and a third stageiiip-iiop 74. The register 12 includes a first stage flip-dop 78, asecond stage hip-flop 8,2 and a third stage ilip-ilop S6. Inputs X1, X2and X3 are applied to the flip-flops 5G, 70 and 74 of Athe register lll,and inputs Y1, Y2 and Ya are applied to the llip-ilops 7S, 82 and S6 ofthe register 12. These flip-flops, as are the remaining flip-flops:illustrated through the various iigures in the drawings, areessentially identical and therefore only one llip-ilop, the ipilop Si),is illustrated in detail.

The tiip-op Sti of the register 10 shown in FG. 4 includes two paths orlines 52 and 54. Current is present 1n one of these lines 52 or 54 tothe exclusion of the other upon the application of a Zero or a Onesignal to the X1 input. When the X1 input is a One, there is currentfrom a terminal S15 to a terminal 6d which causes the cryotron orinhibitor 62 to inhibit current from a terminal 55 through the line 54.Hence, there is current from the terminal 56 through the line 52,-through an inhibitor 64 and through an inhibitor 65. When there iscurrent through the inhibitor 65 this inhibitor blocks current throughthe line 54. Therefore, the One input applied to Ithe terminal 5S may beremoved if desired since now the current through the line 52 causes theinhibitor 66 to block current .through the line 54. The line 52 may becalled the One line of the dip-liep since current is caused through thatline when a One is applied to the flip-liep 5G. When a Zero is appliedto the X1 terminal 68, current through the line 52 is inhibited, and a.current is present from the terminal 55 through the line 54. Althoughthe X1 input lines are illustrated as horizontal and the X2, X3, Y1, Y2and YS lines are shown `as vertical, this is done for simplicity ofillustration and all of these lines are equivalent.

' Only three stages are illustrated in each of the registers 10 and 12,but it will be readily apparent after a description of the entire addercircuit that any number of these stages may be employed in circuitsconstructed in accordance with the principles of the present invention.Each of the hip-flops of the registers 10 and 12 has a pair of outputlines which include a One output line and a Zero output line. Thesepairs of lines are coupled with vertical pairs of lines in the adderinput array 14 of FiG. 5 to control the diversion of currents in thehorizontal pairs of lines of the adder input array.

Referring now to FIG. 5, the adder input array 14 is shown connected tothe upper half of the stepping switch 16. The adder input array 14includes three pairs of vertical Wires 10th; and 101th, 161211 and 1mb,and 10411 and 1Mb which are connected to the flip-flops Sil, 7i) and 74,respectively, of the register 19 of FIG. 4. Three pairs of verticalwires 10611 and 1Mb, 10311 and b, and 110:1 and 11011 are respectivelyconnected to the iiip-ops 78, 82 and S6 of the register 12 of FlG. 4.Each lefthand wire of the pairs of vertical wires of the adder inputarray 14 is connected to the One side of the corresponding Hip-flop ofFIG. 4. Each righthand wire of these pairs of Wires is connected to theZero side of the corresponding dip-ilop of FIG. 4. Three pairs ofhorizontal wires 11211 and 11211, 11411 and 11411, and 116e and 116b ofthe adder input array 14 are associated with the register 16 of FG. 4and are coupled with the step ping switch 15. Three pairs of horizontalwires 11811 and 11810, 12Go and 12%, and 12211 and 122!) are associatedWith the register 12 of FIG. 4 and are coupled with the stepping switch16. The vertical lines 19611 and lilb, 19211 and 1112!), and 104:1 and1t`14b are connected to output terminals 101), 1112 and 164,respectively. The Vertical l-ines 166e and 1116!), Mrz and 1981), and11051 and 11% are connected to output terminals 1116, 108 and 119,respectively. The horizon-tal lines 11211 and 112i), 11411 kand 1Mb, and11611 and 116i) of the adder input array 14 are connected to thestepping switch 16 through lines 112., 114 and 116, respectively. Thehorizontal lines 11811 and 11811, 12011 and 12%, and 12.211 and 121211of the adder input array 1d are connected to the stepping switch 16through lines 112, 114 and 116, respectively.

The upper half of the stepping switch 16 shown in FIG. 5 includes aselector switch 130. The selector switch includes tour switches R1, R2,R3 and R4. The switches R1 through R1 connect an input terminal 132. tofour vertical lines 134, 136, 13S and 14d, respectively. These verticallines 134, 136, 133 and 140 extend to a common output terminal 142(illustrated in FIG. 7). The switches R1 through R4 are illustrated asmechanical type switches because it is believed that this type ofrepresentation provides a more graphic illustration of their operation.However, it is to be understood that these switches are preferablysupereonductive devices similar to those disclosed herein. The switchesR1 through R4 areoperated one at a time, tha-t is, only one of theseswitches is open at any time. Current is nonnially present from theterminal 132 through each of the closed switches. During an addingoperation of two three-bit binary numbers applied to the registers 16and 12 (HG. 4), R1 is opened, R2 is opened and R1 is closed, R3 isopened and R2 is closed and R4 is opened and R3 is closed.

In the operation of the adder input array 14, current is initiatedsequentially through either the left-hand (One) or the right-hand (Zero)vertical wire of each of the six pairs of vertical wires depend-ing uponthe state of each of the iiip-fiops of FIG. 4 connected to these pairsof vertical wires. According lto a feature of this invention, when thereis current through any one o these vertical wires, the inhibitor on avertical wire inhibits current through a horizontal wire crossing thatparticular inhibitor. For example, assume cuirent through the verticalline 101111 and through the vertical line 10611 as is the case when theflip-Hops 50 and 7S of FIG. 4 are in the One ystate (a binary One hasbeen applied to the iirst stages of the registers 1d and 12 of FIG. 4).The swi-tch R1 is now opened and there can be no current from theterminal 132 through the line 134 of the stepping switch 16 and,therefore, inhibitors 154 and 156 do not inhibit current in lines 112and 118. There is current from a terminal 144 through the inhibitor 154and through the line 112, and also from a terminal 145 through theinhibitor-156 and the line 113. Since there is current through thevertical lines 113911 and 19611, inhibitors 158 and 152 cause current tobe inhibited from the horizontal lines 1121b and llb, respectively.Hence, lthere is current in the line 112 through the line 11211 to an XOne output line 15S. There is current in the line 118 through the line11811 to a Y One output line 169. Conversely, if there is currentthrough the Zero lines 10011 and 106b instead of through the One lines1116s and 10611, inhibitors 162 and 164 would inhibit current in thelines 11211 and 11811, respectively. In this case there would be currentapropos from the line 112 through the line 112i: to an X Zero outputterminal 166 and also current from the line 118 through the line 118i?to a Y Zero output terminal 168.

As a further illustration of the operation of the adder input array 14assume that the switch R2 is open, that the switch R1 is closed, andthat there is current through the Zero line 10211 and the Zero line 108b(as is the case when the ip-ops 70 and 82 of FIG. 4 are in the Zerostate). Inhibitors 170 and 172 inhibit current in the lines 11411 and12011, respectively. Current is present from the terminal 144 through aninhibitor 174, .the line 114, the line 114b to the Y Zero output line166. There is also current from the terminal 146 through an inhibitor176, the line 120, the line 120b to the Y Zero output line 168. It isbelieved that the operation of the entire adder input array 14 andstepping switch 16 is apparent from the above description. The remaininginhibitors in the adder input array 14 and in the stepping switch 16operate in a similar manner to divert current from certain horizontallines lthrough two particular horizontal lines to the X output lines 158or 166 and the Y output lines 160 or 168.

Any three bit binary number may be applied to each of the registers and12 of FIG. 4. By the operation of the switches R1 through R4 the X1 `andthe Y1 bits (from the rst stages of the registers 10 and 12,respectively) are gated to the X and Y output lines of the adder inputarray 14 followed by the X2 and the Y2 bits, and the X3 and the Y3 bits.If more input stages are desired in the registers 10 and 12 of FIG. 4pairs of vertical lines for each additional stage in each registercorresponding to the pairs of vertical lines 10011 and b, 106aand b,18211 and b, 10811 and b, 10411 and b, 11011 and b are added to theadder input array 14 of FIG. 5. Also, additional pairs of horizontallines corresponding to lthe lines 11211 and b, 11811 and b, 11411 and b,12011 and b, 11611 and b and 12211 and b with their associated steppingswitch lines 112, 118, 1114, 120, 116 and 122, respectively, are used.It should now be apparent that for each additional stage added in eachof the registers 10 and 12 corresponding pairs of honizontal andvertical lines are required. Lines 180 and 182 are included inthestepping switch 16 and the adder input array 14 to provide an X =Y=0output from the adder input array 14 and, consequently, an input to theadder array illustrated in FIG. 6 to gate through the final carry signalto the highest stage (the fourth as illustrated) of the sum register 22.The X and Y outputs from the lines 158 and 166, and the lines 160 and168, respectively, of the adder input array 14 are applied tocorresponding horizontal lines in the adder array illustrated in FIG. 6.

The adder array includes the X input lines 158 and 166 and the Y inputlines 160 and 168 all of which are coupled from the output of the adderinput array 14 shown in FIG. 5. The adder array 18 includes another setof horizontal lines 200v and 202 which provide input `carry bits C tothe adder array. Four sets of vertical lines intersect the X, Y and Chorizontal lines. The rst set of these lines 20411, 20411, 20de and2041i provides a sum output bit or signal S of One. The second set ofthese lines 20611, 26615, 286C and 20611 provides a sum output bit S ofZero. The third and fourth sets of the vertical lines of the adder array18 include lines 208a, 208]), and 208C for providing a carry output bitC' of One, and lines 21011, 2106 and 210e for providing a carry outputbit C' of Zero.

The X, Y and C input currents to the adder array 18 of FIG. 6 arepresent on the horizontal lines to output terminals 212, 214 and 216,respectively. The sum output currents S are present on the vertical sumlines 20411 through d and 20611 through d to the output lines 204 and206. I1 `he output carry signals C flow from the terininal 228 throughthe vertical carry lines 20811 through c and 21011 through c to theoutput carry lines 208 and 210. According to another aspect of thisinvention, input currents in 4the One or the Zero lines of the X, Y andC inputs (158 and 166, 160 and 168, and 200 and 202, respectively) causeall but one of the sum lvertical lines 20411 through d and 20611 throughd to be inhibited, and all but one of the carry output lines 201811through c and 21011 through c to be inhibited. In other words, the inputsignals X, Y and C cause particular output lines top b'e inhibitedthereby leaving certain superconductive lines through which output sumbits S and carry bits C may flow.

The following truth tab-le, Table' I, illustrates the eight possibleinputs vto the X, Y and C input lines of the adder array 18 alongvwiththe resulting output sum sig"- nals S and carry signals C.

TabZeI Inputs Outputs Assuming the condition number 1 illustrated in theabove table, when X is a Zero', there is current through Vthe horizontalline 166 of the adder array 18 shown in FIG. 6; when Y is a One, thereis current through the horizontal line 160; and When C is a One, thereVis current through the horizontal line 200'. Current through thev line166 causes inhibitors 230, 232, 234, 236, 238 and 240 to inhibit currentin the vertical lines 20411, 2041i, 206k, 206e, 20811 and 208]),respectively. Current through the line 160 causes inhibitors 250, 252,254, 256, 258 and 260 to inhibit current through the vertical lines204b, 2041i, 20611, 206e, 21011 and 210C, respectively. Current throughthe line 200 causes inhibitors 270', 272, 274, 276, 278 and 280 toinhibit current through the vertical lines 210e', 210b, 206]), 20611,20411 and 204C, respectively. Current is not inhibited in lines 2061iand 208e. Current is present from the terminal 218 through the verticalline 2061i and through the surn S Zero output line 206. There is' alsocurrent from' the terminal 220 through the vertical line 208e andthrough the carry C' One output line .208'. Hence, when X is a Zero, Yis a One, and C is a One, the adder array 18 generates a sum bit S ofZeroA aud a carry bit C of One. Y l

For the second condition illustrated in the above Table I, the X inputbit is a Zero, 4the Y input bit is a Zero, and the carry input bit C isa One. As noted above, when the X input bit is a Zero, there is currentthrough the horizontal line 166, and when the carry input bit C is aOne, there is current through the horizontal line 200'. When the Y inputbit is arZero, there is current through the horizontal line 168. Currentthrough the horizontal line 166 causes the inhibitors on that line toinhibiteur rent through the vertical lines 20411, 2041i, 2Mb', 206C,20811 and 208k. Current through the horizontal linev 168 causes theinhibitors on that line to inhibit'current through the vertical lines20411, 204C, 206i), 2061i, 20811 and 208e. Current through thehorizontal line 200 causes the inhibitors on that line to inhibitcurrent through the vertical lines 210e, 210b, 216i), 20611, 204d and204C. All of the vertical lines are inhibited except the line 20411 and21011. Hence, current is present through the line 204b and the line 204resulting in a sum output of One, and current is present through theline 21011 and the line 210 resulting in an output carry of Zero. Theadder array 18 is operat-y ed in a similar manner for the remainingconditions illustrated in the above Table I, and it is believed that theoperation of the adder array is obvious for these remaining conditions.

aoraoss It is now apparent that Zero or One input bits to the X, Y and Cinputs of the adder array 13 cause current to be inhibited throughcertain of the vertical lines of the array thereby providing One or Zerosum S and carry C output bits. The carry output bit C' is applied to acarry storage circuit illustrated in FG. 8, and the carry input bit C isprovided from the carry storage` circuit as will be explainedhereinafter. The sum output bit S of the adder array is applied to anadder output array 2b illustrated in FIG. 7 through lines 204 and 286.

Referring now to FIG. 7, the adder output array 20, the sum register 22and the lower half of the stepping switch 16 are illustrated therein.The sum S One line 294 is connected to four horizontal lines .'iii, SGZ,304, and 306 and the sum S Zero line 26 is connected to horizontal lines310, 312, 314 and 316. The horizontal lines 300, 302, 304 and 306 areconnected to like numbered lines in the stepping switch 16. Thehorizontal lines 310, 312, 314 and 316 are also connected to likenumbered lines in the stepping switch 16. Four pairs of vertical linesintersect the horizontal lines in the adder output array 20, and thesevertical pairs of lines are connected to four ip-iiops in the sumregister 22. These pairs of vertical lines are numbered 33th: and 330i),335.20 and 332i?, 334a and 334i?, and 336a and 336B and are connected tothe Hip-flops 349, 342, 344 and 34:6, respectively, in the sum register22. Y Y g According to another feature of this invention, in theoperation of the adder output array 2?v a sum input bit S on line 204 or2do together with the operation of the stepping switch 16 causes thatsurn bit S to be gated through the adder output array 2t? and to bestored in one of the flip-Hops of the sum register 22. For example,assume that the switch R1 of the upper half of the stepping switch 16illustrated in FIG. 5 is open. Thereis then no current through the line134 to the output terminal 142 of the lower half of the stepping switch16 illustrated in FIG. 7. Since there is no current through the line 134of the stepping switch 16, current through the line 39? is not inhibitedby the inhibitor 360. Assume also that a sum input bit S of One isapplied on line 264 to the adder output array 20. Current is presentthrough the line 204, the line 300, an inhibitor 36) to an outputterminal 350. There is no current through the lines 302, 304 and 306since current through these lines is blocked by inhibitors 362, 364 and36:5. Currentthrough the line 300 causes an inhibitor 376) to blockcurrent through the vertical line 330b. There is then current throughthe Vertical line 33M to the One side of the hip-flop 34) of the sumregister 22. This causes the iiip-tlop 34? to switch to the One state ifit was previously in the Zero state (which is the usual case since thehip-flops of the sum register 22 are initially set to Zero) or causes itto remain in the One state if it was previously in the One state. Notethat current through the remaining vertical lines 332:1 and b, 334:1 andb, and 336e and b is not inhibited at this time by a One input on theline 2M. However, the hip-flops 342, 344 and 346 of the sum register 22are previously set, and since there is no current through the horizontallines 302, Still, 306, 310, 312, 314 and 316, the states of theseremaining iiip-lops 342, 344 and 346 are not altered.

Inputs to the adder output array 20 in combination with the operation ofthe stepping switch 16 operate to store the sum bits S applied to theadder output array 20 in the ip-iiops of the sum register 22 in the samemanner as described above. As a further example, assume that a Zero suminput bit S is applied through the line 206 and that the switch R1 isstill open. There is current through the line 206, the line 310 and aninhibitor 330 to an output terminal 352 in the stepping switch 16.Current through the inhibitor 380 inhibits current through the verticalline 330:1 and consequently there is current through the vertical line33tlb to the Zero side of the iiipop 340. In a like manner sum bits Sproduced as a result of the X and the Y input bits applied to theregisters 10 and 12 of FIG. 4 in the higher stages (stage 2, stage 3,etc.) are stored in the higher stages of the sum register 22 as theswitches R1 through R., of FIG. 5 are operated. In other Words, X1 andY1 input bits to the registers 16 and 12 of FIG. 4 are gated through theadder input array 14 of FIG. 5 to produce a sum bit S in the adder array18 of FIG. 6. The sum bit S produced by the adder array 13 is applied tothe adder output array 20 of FIG. 7 and stored in the rst stage of thesum register 22 when the R1 switch of the stepping switch 16 of FIG. 5is open. In a like manner, the operation of the switches R2, R3 and R4causes sum bits S to be stored in the second, third and fourth stages ofthe sum register 22.

Referring now to FIG. 8, a carry storage circuit is illustrated forstoring the carry bit C generated in the adder array 18 of FIG. 6 andsubsequently applying this stored carry bit as Vthe input carry bit C tothe adder array 13. The carry storage circuit includes a gate 36@connected to a hip-hop B. The flip-lop B is connected to a gate 3&2which is connected to a iiip-ilop A. The output carry lines 238 and 21@from the adder array 1S of FIG. 6 intersect three horizontal linesStili, 366 and 36S within the gate 3%. A pair `or". vertical lines 310and 312 intersect the horizontal lines 3134, 3%6 and 3% in the gateEdit. The pair of vertical lines 316 and 312 are con nected respectivelyto the One and to the Zero terminals of the input P.

rEhe P input to the gate 3%@ controls the storage of the carry signalsignal C in the iiip-ilop B. When the P input is a Zero inhibitors 32hand 322 inhibit current through the horizontal lines 3% and 3426 therebycausing current through the line 364. Since no current may exist in theVhorhiontal lines 3:96 and 3% the carry bit C cannot set the hip-flop B.When the P input is a One, current is not inhibited in the horizontallines 396 and 33S and the generated carry signal C' is stored in theflip-hop B. Assuming that the generated carry signal C is a One, currentthrough the line 26S to an output terminal 324 causes an inhibitor 326to block current through the horizontal line 3%. The only uninhibitedcurrent path through the horizontal lines of the gate 3th? is the lineHence, current through the line 368 causes an inhibitor 33t? to inhibitcurrent through a line 332 of the hip-flop B. Current through a line 334of the ilip-lop B sets that hip-flop in a One state. Conversely, if thegenerated carry signal C' is a Zero, current through the horizontal line3tl6 thereby causes current through the line 332 of the flip-hop B thussetting the flip-flop B in the Zero state.

The output of the fip-fiop B on the lines 332 or 334 along with an inputQ on a line '3d-i3 or 342 controls the transfer of the carry bit fromthe flip-hop B to the flipiiop A. The gate 3492 is constructed the sameas the gate 3%, and both of these gates operate in a similar manner.When a Zero is applied to the input Q, there is current through a line341i thereby causing current through the horizontal lines 344 and 346 tobe inhibited by the inhibitors 34S and 353, respectively. Since one ofthe horizontal lines 34d or 346 must be uninhibited for a transfer ofthe carry bit from the Hip-iop B to the ilipilop A no transfer of thisbit occurs. When a One is appiied to the Q input, the carry bit storedin the flip-Hop B is transferred to the hip-Hop A. Assuming that a Oneis stored in the flip-hop B and that a One is applied to the Q input,there is then current through the line 334 to cause m inhibitor 352 toinhibit current in the horizontal iine 344. Current is present onlythrough the horizontal line 346 thereby causing an inhibitor 356 toinhibit current in the line 262. Current through the line 200 sets theflip-flop A, and current through the line 2113i) is taken to indicatethat the flip-flop A is in the One state.

AEach time two X and Y bits are added in the adder array 18 of FIG. 6 acarry bit C is generated and this carry bit is applied to the gate 36hof the carry storage circuit of FIG. 8. A One is applied to the P inputand the generated carry bit C' is stored in the tiip-op B. During theaddition of the second X and Y bits a One is applied to the Q inputwhich causes a transfer of the carry bit stored in the tiipdiop B to theflip-dop A. The

carry bit stored in the iiip-op A is applied as the carry C input to theadder array 18 of FIG. 6. A sum bit is generated by the adder array 1Sand stored in the sum register 22 of FG. 7, and a new carry bit C isgenerated. By switching the P input to a One this generated carry bit Cis stored in the flip-hop B. During the addition of the third X and Ybits the carry signal stored inthe flipop B is transferred to thetiip-iiop A, a sum bit is stored, and a new carry bit is generated. Thecarry storage circuit of FiG. 8 operates in a similar manner for eachsucceeding combination of X and Y inputs to the adder array 18 of FlG.6. It is now seen that the carry storage circuit of FiG. 8 stores thecarry bit generated during the addition of an X and a Y bit, andtransfers this stored carry bit to the input of the adder array 1?during the next succeeding addition of an X and a Y bit.

The operation of the adder of the present invention is now describedwith reference to FIGS. 4 through 8. Note that FIG. 2 illustrates therelationships of FIGS. 4 through 8. According to a further feature ofthis invention, in operating the adder of the present invention inputbits X1, X2 and X3 are stored in the X register 1t) and input bits Y1,Y2 and Y3 are stored in the Y register 12 of FiG. 4. As the switches R1,R2, R3 and R4 of the stepping switch 16 illustrated in FIGS. 5 and 7 aresequentially opened and closed each corresponding X and Y input bit isgated through the adder input array 14 of FIG. 5 and applied to theadder array 13 of FIG. 6 which produces a sum bit S and a carry bit C.The sum bits S generated during the adding operation are gated throughthe adder output array 20 of FIG. 7 and stored in the iirst, second,third and fourth stages of the sum register 22. Each carry bit producedby the adder array 18 of FIG. 6 is stored in the carry storage circuitillustrated in FIG. 8 and subsequently transferred back to the adderarray 18 as an input carry bit C during the addition of the nextsucceeding X and Y bits.

As a specic example of the operation of the adder of the presentinvention, the addition of X=3 and Y=6 will be described. The binarynumbers for these decimal numbers are 011 and llt), respectively. Thesebinary numbers are applied to and stored in the X register 1i) and the Yregister 12. A One is applied to the irst flipiiop Si), a One is appliedto the second iiip-iiop 7) and a Zero is applied to the third iiip-flop74 of the X register 19 of FIG. 4. A Zero is applied to the firstflip-flop '78, a One is applied to the second iiip-op 82 and a One isapplied to the third ip-tlop 86 of the Y register 12. The

vip-iiops A and B and the flip-flops of the sum register 22 are all setto Zero. The adder is now set to add the two binary numbers stored inthe registers 10 and 12.

The switch R1 of the stepping switch 16 is opened and the rst X and Ybits One and Zero, respectively, are gated through the adder input array14 and are applied to the adder array 1S. The adder array 18 produces aOne sum bit S and a Zero carry bit C. The One sum bit S is gated throughthe adder output carry 2t) and store-d in the iirst iiip-iiop 340 of thesum register 22. The carry bit C for the addition of the iirst two X andY bits is a Zero. A One input is applied to the P input and thegenerated Zero carry bit C is stored in the flip-flop B. The switch R1is closed as the switch R2 is opened. A One input is applied to the Qinput and the stored Zero carry bit in the dip-flop B is transferred tothe flip-Hop A.

When the switch R2 is opened, the second X bit (a One) and the second Ybit (a One) are each gated through the adder input array 14 and appliedto the adder array 1S. The carry input bit C applied to the adder array18 is a Zero at this time since there was a Zero carry from the previousoperation. A Zero sum bit S is generated by the adder array 18, gatedthrough the adder output array 2t) and stored in the second iiip-flop342 of the sum register 22. A One carry bit C is generated by the adderarray 18, and a One is applied to the P input to store this One carrybit in the iiip-fiop B. The switch R2 is closed as the switch R3 isopened. A One is applied to the Q input which causes the carry bit ofOne stored in the B flip-flop to be transferred to the A flip-flop. Whenthe switch R3 is open the third X bit (a Zero) and the third Y bit (aOne) are each gatedthrough the adder input array 14 and applied to theadder array 18. The adder array 18 generates a Zero sum bit S which isgated through the adder output array 20 and stored in the third flipop344 of the sum register 22. The adder array 1S generates a One bit C'. AOne is applied to the P input and the One carry bit C is stored in the Bp-iiop. The switch R3 is closed as the switch R4 is opened. A One isapplied to the input Q and the One carry bit stored in the B tiip-iiopis transferred to the A ip-iiop.

When the switch R4 is open there is current from the terminal 144through the horizontal line 180 to the Zero X line 166 and also from theterminal 146 through the horizontal l'ne 182 to the Zero Y line 168.Hence, at this time Zero X and Y bits are applied to the adder array 18to gate through the final carry bit C of One. The adder array 1Sproduces a One sum bit S and this bit is gated through the adder outputarray 2d and stored in the fourth flip-dop 346 of the sum register 22.The adder array 18 also generates a Zero carry bit C which is stored inthe B fiip-op by applying a One to the P input. The adding operaton ofthe X and Y numbers is now complete and the result is stored in the sumregister V22, as 1GO-l which is equal to the decimal number 9. Theoperation of the adder of the present invention is now apparent. Theoperation for adding other numbers is similar to that set forth aboveand it is believed that the above illustration is suiiicient for anunderstanding of how to add any desired binary numbers.

It is now seen that the present invention provides a cryogenic serialadder employing rectangular array inhibitor logic. Input bits to beadded are stored in input storage registers and signals from the inputstorage registers, along with a stepping switch, cause all but certainlines of an adder input array to 'be inhibited. Currents are presentthrough the remaining lines of the adder input array to an adder arraythereby causing certain output lines of the adder array to be inhibited.A carry input signal or bit is applied to the adder array therebycausing additional output lines of the adder array to be inhibited.Currents are present through the remaining output lines of the adderarray as sum and carry bits. The generated carry bit is stored andsubsequently applied as an input to the adder array during the additionof the next set of bits. The sum bit is stored in a desired sum storagedevice when `the stepping switch inhibits storage in all but the desiredstorage device. v Although a three stage cryogenic serial binary adderis described and illustrated, it is to be understood,las pointed out inthe above description, that more binary stages may be employed withoutdeparting from the principles of the presen-t invention. The inventionis not limited to cryotron inhibitor circuits since numerous inhibitordevices may be employed in -adderrs constructed and operated accordingto the principles of inhibitor logic described. Furthermore, theinvention is not limited to binary adders. Adders may be constructedaccording to the principles ofthe present invention which operate withany desired radix by changing the arrays and circuits herein illustratedto accommodate more inputs and outputs (three, four, etc.).

What is claimed is:

l. A serial adder employing rectangular array inhibitor logiccomprising: a iirst register having a plurality of stages with aplurality of outputs; a second register having a plurality of stageswith a plurality of outputs; an adder array including a plurality ofinteracting lines having inhibitors placed at selected points ofinteractions; first means to apply the outputs ot corresponding stagesof the iirst and the second registers to the adder array whereby currentliow in certain of saz'd lines is inhibited to provide sum and carryoutput signals from other of said lines; second means to store sumoutput signals; third means to store a carry output signal; whereby saidserial adder sequentially adds the outputs from each corresponding stageof the rst and the second registers and provides sum output signals andcarry output signals, said second means stores said sum output signals,and said third means stores and sequentially applies said carry outputsignals to said adder array.

2. An adder employing rectangular array inhibitor logic comprising: aiirst input circuit and a second input circuit each of which has aplurality of stages with a plurality of outputs; each of said stageshaving a given number of outputs related to the radix employed; an adderarray having a plurality of current paths; means to apply sequentiallycorresponding outputs of said inputcrcuits to said adder array toinhibit currents in selected Ycurrent paths therein; said ladder arrayproviding a sum signal and a carry signal as each of said correspondingoutputs is applied thereto; means to store each of said sum signals;means to store each of said carry signals and subsequently to -applyeach of said carry signals to said adder array as said correspondingoutputs are sequentially applied there- 3. An adder employingrectangular array inhibitor logic as in claim 2 wherein the number ofoutputs of each of said stages is two and said radix is two.

4. A cryogenic serial adder employing rectangular array inhibitor logiccomprising: a iirst input circuit and a second input circuit each ofwhich has a plurality of outputs; a rst array, a switching array; anadder array; means coupling the outputs of each of said input circuitsto said first array; means coupling said switching array to said firstarray; means coupling said first array to said adder array; a secondarray; means coupling said adder array to said second array; meanscoupling said switching array to said second array; a carry circuit;means coupling said carry circuit to said adder array; whereby inputsigg nals applied to said lirst array and control signals from saidswitching array cause said input signals to be added sequentially insaid adder array, said adder array applying a sum signal to said secondarray and a carry signal to said carry circuit, and said carry circuitapplying said carry signal to said adder array.

5. A cryogenic binary serial adder employing rectangular array inhibitorlogic comprising: a rst group of input storage devices each havinginputs and groups of outputs; a second group of input storage deviceseach having inputs and groups of outputs; a first array including aplurality of groups of vertical lines and a plurality of horizontallines having inhibitors placed at selected Vpoints of interaction ofsaid lines; means to apply current sequentially to said horizontallines;

an adder array including a plurality of' vertical lines and a pluralityof horizontal lines having inhibitors placed at selected points ofinteraction of said lines; means coupling said groups of outputs of saidstorage devices to said groups of vertical lines of said rst array;means connecting the horizontal lines of said iirst array to certain `ofthe horizontal lines of said adder array; means applying current Ytosaid adder array, a carry circuit coupled to certain of the verticallines and other horizontal lines of said adder array; an output storagecircuit coupled to other vertical lines of said adder array; wherebyoutput signals from said groups of ouputs cause current through selectedones of the horizontal lines of said lirst array to be inhibited therebyallowing current through certain of the horizontal lines of said adderarray, and said carry circuit causes current through other horizontallines of said adder array causing current to be inhibited in selectedvertical lines of said yadder array thereby allowing sum and carrycurrents in the remaining vertical lines of said adder array.

6. A cryogenic serial adder employing rectangular array inhibitor logiccomprising: a iirst group of storage devices having input lines andoutput lines, a second group of storage devices having input lines andoutput lines, a rst array including a plurality of vertical lines and aplurality of horizontal lines having inhibitors placed at selectedpoints of interaction of said horizontal and vertical lines, means toapply current sequentially to the horizontal lines of said iirst array,means connecting the output lines of said first group of storage devicesto a portion of the vertical lines of said first array, means connectingthe output lines of said second group of storage devices 'to theremaining vertical lines of said iirst array, an adder array including aplurality of vertical lines and a plurality of horizontal lines havinginhibitors placed at selected points of interaction oi said line, meansconnecting the horizontal lines of said first array to certain of thehorizontal lines of said adder array, means to apply current to thevertical lines of said adder array, a carry storage circuit having inputlines and output lines, means connecting certain of the vertical linesof said adder array to the input lines of said carry storage device,means connecting the output lines of said carry storage device to theremaining horizontal lines of said adder array, an output storage devicecoupled to the remaining vertical lines of said adder array, wherebyoutput signals from said rst and second groups of storage devicesestablish current in selected ones of the vertical lines of said firstarray thereby inhibiting current through certain horizontal lines ofsaid first array and diverting current through certain other horizontallines of said first array, whereby current is established in certainhorizontal lines of said adder array which in turn inhibits current fromilowing in certain vertical lines of the adder array and permits currentthrough other vertical lines of said adder array, said carry storagecircuit establishing current in certain other horizontal lines of saidadder array which causes current to be inhibited from selected verticallines of said adder array whereby currents representing sum and carrymay iiow in the remaining vertical lines of said adder array.

7. The apparatus of claim 6 wherein the means to apply currentsequentially to said horizontal lines of the first array is a cryogenicstepping switch.

References Cited in the file of this patent Buck: The Cryotron--ASuperconductive Computer Element, Proceedings of the IRE, vol. 44, pages482-493, No. 4, April 1956.

Richards: Arithmetic Operations in Digital Computers, D. Van Nostrandand Co. Inc., Princeton, NJ., March 17, i955, page 129, Figures 4-30.

1. A SERIAL ADDER EMPLOYING RECTANGULAR ARRAY INHIBITOR LOGICCOMPRISING: A FIRST REGISTER HAVING A PLURALITY OF STAGES WITH APLURALITY OF OUTPUTS; A SECOND REGISTER HAVING A PLURALITY OF STAGESWITH A PLURALITY OF OUTPUTS; AN ADDER ARRAY INCLUDING A PLURALITY OFINTERACTING LINES HAVING INHIBITORS PLACED AT SELECTED POINTS OFINTERACTIONS; FIRST MEANS TO APPLY THE OUTPUTS OF CORRESPONDING STAGESOF THE FIRST AND THE SECOND REGISTERS TO THE ADDER ARRAY WHEREBY CURRENTFLOW IN CERTAIN OF SAID LINES IS INHIBITED TO PROVIDE SUM AND CARRYOUTPUT SIGNALS FROM OTHER OF SAID LINES; SECOND MEANS TO STORE SUMOUTPUT SIGNALS; THIRD MEANS TO STORE A CARRY OUTPUT SIGNAL; WHEREBY SAIDSERIAL ADDER SEQUENTIALLY ADDS THE OUTPUTS FROM EACH CORRESPONDING STAGEOF THE FIRST AND THE SECOND REGISTERS AND PROVIDES SUM OUTPUT SIGNALSAND CARRY OUTPUT SIGNALS, SAID SECOND MEANS STORES SAID SUM OUTPUTSIGNALS, AND SAID THIRD MEANS STORE AND SEQUENTIALLY APPLIES SAID CARRYOUTPUT SIGNALS TO SAID ADDER ARRAY.